The present invention relates to domino logic circuits. More particularly, the present invention relates to a method of automatically mapping a digital logic design onto a domino logic library.
Domino logic is a precharged CMOS logic family first introduced in 1982. The logic style has inherent speed advantages over static logic leading to its use in microprocessors and other high performance digital blocks. The speed advantages of domino logic are accompanied by much greater design complexity, as well as increased integrated circuit die area and power consumption. Standard ASIC tools are not designed to accommodate domino logic timing models and behavior. This has limited the use of domino logic to custom and structured custom design flows. In recent years the increasing consumerization of electronics has forced time-to-market and cost considerations to become a major factor in design choices. Both of these factors, obviously, limit the use of domino logic.
As discussed, the use of domino logic in a logic circuit results in an improvement in operating speed, up to 1.5 times or more when compared to an equivalent static logic circuit. There are, however, some disadvantages with a domino logic synthesis solution including greater integrated circuit die area and power consumption.
Prior automated mapping solutions for domino logic designs support only a simplified library (non-inverting functions and basic sequential cells), which leads to sub-optimal results when synthesizing with traditional tools like Synopsys Design Compiler® or Cadence RTL Compiler®. Also, very often, the function to be mapped onto a domino logic circuit has to be extracted and implemented separately, which implies a logical re-partitioning and a new interface management.
What is desired, therefore, is a mapping method for a domino logic design that does not include the aforementioned limitations with prior art mapping methods.